- ... literals.1
- Due to the strongly typed characteristic of VHDL it
can be necessary to specify the type of a value explicitly:
character'('1') |
bit'('1') |
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- ... defined.2
- The types character, bit and boolean are predefined as enumeration types in the package
STANDARD.
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- ... processes.3
- Due to the
importance of signals in VHDL they are given a more detailed
description in Section 7.
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- ... types.4
- Functions are described in Section 6.2, page
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- ... irrelevant.5
- Additional information on process-statements and their execution during the simulation is
found in Section 8, page
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- ... circuit6
- Section 7.2
(page
) explains the way wait-statements
work in greater detail.
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- ... defined.7
- There is no standard bit_vector addition in VHDL!
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- ... statements.8
- See section 6, page
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- ... architecture.9
- In the
following examples, generics are used to specify delay times in
structural descritions. Similarly, they can be used as constants for
the description of behavior (process).
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