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Contents
University of Ulm
Department of Microelectronics
VHDL Manual
Richard Geißler
Slavek Bulach
September 1998
Contents
1. Introduction
1.1 Motivation: IC Design Methodologies
1.2 Contents and Structure of this Manual
2. Basic VHDL Concepts
2.1 Components of a VHDL Model
2.2 Entity Declaration
2.3 Architecture
2.3.1 Concurrent Behavioral Description
2.3.2 Sequential Behavioral Description
2.3.3 Structural Description
2.4 Configuration Declaration
2.4.1 Configuration of Behavioral Descriptions
2.4.2 Configuration of Structural Descriptions
2.5 Packages
2.5.1 Package Declaration
2.5.2 Package Body
2.5.3 Important Packages
2.6 Additional Signal Characteristics
2.6.1 Delay Models
2.6.2 Resolution Functions
2.7 Analysis of VHDL Models
2.8 Simulation
3. Data Types
3.1 Scalar Types
3.2 Composite Types
3.3 Access Types
3.4 File Types
3.5 Type and Field Attributes
4. Declarations and Identifiers
5. Expressions and Operators
6. Sequential Modeling
6.1 Assignments
6.2 Subprograms
7. Signals
7.1 Signal Declaration
7.2 Signal Assignments in Process
7.3 Implicit Type Resolution and Drivers
7.4 Signal Attributes
8. Concurrent Modeling
9. Structural Descriptions
9.1 Generation of Instances
9.2 Use of Packages
9.3 Configurations
9.4 Generics
10. Packages and Libraries
Appendix
11. Package TEXTIO
About this document ...
Richard Geissler
1998-10-07