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6. Sequential Modeling

A process plays the central role in sequential VHDL descriptions. The process-Statement is used for behavioral descriptions of architectures. It defines code segments where internally all statements are processed in sequence, one after another.

Process-Statements behave like concurrent statements with respect to the rest of a design. At any given time there may be many different processes active, and their order of execution in VHDL code is irrelevant.5  

Syntax:
[proc_label:] process [(sensitivity_list)]
  
[subprogram_decl|subprogram_body]
  
[type_decl]
  
[subtype_decl]
  
[constant_decl]
  
[variable_decl]
  
[file_decl]
  
[alias_decl]
  
[attribute_decl]
  
[attribute_spec]
  
[use_clause]
begin
  
[sequential_statements]
end process
[proc_label];

Note that the optional label (proc_label) is extremely useful for debugging purposes during the simulation, and therefore should not be omitted.

The example below demonstrates the use of two processes to determine the maximum and minimum values which appear on the input ports.

Example:
entity LOW_HIGH is
  port (  A, B, C: in integer;                
Inputs
          MI, MA: out integer);              
Outputs
end LOW_HIGH;

architecture BEHAV of LOW_HIGH is
begin
  L: process                            
find minimum
    variable LOW: integer := 0;
    begin
      wait on A, B, C;
      if A < B    then LOW := A;
                  else LOW := B;
      end if;
      if C < LOW  then LOW := C;
      end if;
      MI <= LOW after 1 ns;
    end process;
  

  H: process                            
find maximum
    variable HIGH: integer := 0;
    begin
      wait on A, B, C;
      if A > B    then HIGH := A;
                  else HIGH := B;
      end if;
      if C > HIGH then HIGH := C;
      end if;
      MA <= HIGH after 1 ns;
    end process;
end BEHAV;



 
next up previous contents
Next: 6.1 Assignments Up: Contents Previous: 5. Expressions and Operators
Richard Geissler
1998-10-07