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2.7 Analysis of VHDL Models

Once the VHDL description of an electronic system is complete, the next step within the design flow is to simulate the system in order to verify the correct functionality. The second step is to synthesize a gate level netlist for the target technology. In both cases the VHDL models have to be analyzed, which is similar to the compilation in other programming languages like C. From the circuit developer's point of view, the most important action during the analysis process is the checking of the used syntax. The output data generated by this process are stored in design libraries.

A design library is a directory on the computer system where certain analyzed designs are stored. Due to the fact that the path to this physical location depends on the installation of the VHDL system and is usually different for different hosts, logical library names (STD, IEEE, etc.) are used in VHDL descriptions. The mapping of logical library names and the physical storage location is done by the system administrator after installation of the VHDL system. In addition, each user can create personal libraries but then he is responsible for the proper mapping. The concept of logical libraries ensures that VHDL codes are portable. It is highly useful for the exchange of design data.

Many different design libraries may exist simultaneously. Only one of them can be used as the actual working library. The logical name of this library is WORK. Which library is actually used as the design library is defined by settings of the system. During the analysis process all design units are stored in the library WORK. Figure 7 illustrates the library concept.


  
Figure 7: Analysis process.
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During the analysis of VHDL models it is important to follow the proper order. Hierarchical systems have to be analyzed starting from the bottom level to the top. In addition, different design units have to be analyzed in the order shown in Figure 8.


  
Figure 8: Dependencies during analysis.
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next up previous contents
Next: 2.8 Simulation Up: 2. Basic VHDL Concepts Previous: 2.6 Additional Signal Characteristics
Richard Geissler
1998-10-07