Some repetitive structure descriptions, such as elements corresponding to the bus width, memory size, etc., benefit from the array-like arrangement of components. Descriptions of this type may be done with the generate statements, which allow:
1. | repetition of structures corresponding to the for...loop. |
2. | selection of specific instantiations through the if...then conditions. |
Syntax:
generate_label: for variable in range generate
concurrent_statement general instantiations
end generate [generate_label];
generate_label: if (condition) generate
concurrent_statement
end generate [generate_label];
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Example:
entity SHIFT is
port ( SIN, CLK: in bit;
SOUT: out bit);
end SHIFT;
-- iterative construction of a shift register --
architecture NETLIST1 of SHIFT is
component DFF
port (D, CLK: in bit; Q: out bit);
end component;
signal Z: bit_vector (0 to 4);
begin
Z(0) <= SIN;
GF: for I in 0 to 3 generate
UI: DFF port map (Z(I), CLK, Z(I+1));
end generate;
SOUT <= Z(4);
end NETLIST1;
-- separate handling of input and output --
architecture NETLIST2 of SHIFT is
component DFF
port (D, CLK: in bit; Q: out bit);
end component;
signal Z: bit_vector (1 to 3);
begin
GF: for I in 0 to 3 generate
GI1: if (I = 0) generate
U0: DFF port map (SIN, CLK, Z(I+1));
end generate;
GI2: if ((I > 0) and (I < 3)) generate
UI: DFF port map (Z(I), CLK, Z(I+1));
end generate;
GI3: if (I = 3) generate
U3: DFF port map (Z(I), CLK, SOUT);
end generate;
end generate;
end NETLIST2;