In general, processes can communicate with the outside world (other processes, entities...) only through signals, and signal values (for example, output ports) are assigned in processes. There are, however, important factors to keep in mind.
Syntax:
signal_name <= expression [after time_expr {,
expression after time_expr}];
The delay time specified in the signal assignemt (after...)
is considered relative to the simulation time reached before the
assignment. Zero delay time is also allowed. In a single signal assignment
several delays may be given. The simulation algorithm then arranges
the time sequence of the future events in a list (scheduling).
Example:
R <= "
1010"
;
S <= '1' after 4 ns, '0' after 7 ns;
T <= 1 after 1 ns, 3 after 2 ns, 6 after 8 ns;
CLK <= not CLK after 50 ns;
Example:
X <= Y; both assignments will be processed at the wait statement
Y <= X;
the values of X and Y will be exchanged
wait ...
the sequence of these two statements is irrelevant
V := 1; V becomes 1 -- immeditately
S <= V; S will be V (also 1) -- at the wait statement
A := S; A receives the old value of S -- immediately
wait ...
X <= 1; Caution: will be ignored due to the second assignment!
Y <= 3; Y will be 3 -- at the wait statement
X <= 2; this assignment overwrites the first assignment above:
wait ...
X will be 2 -- at the wait statement