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5. Expressions and Operators

Expressions in VHDL may be constructed using the operators listed in the table in order of increasing precedence. The desired precedence may also be achieved through the explicit use of parentheses.



Operator Function Operands Type1 - Type2
Logical Operators
and a $ \wedge$ b bit, bit_vector, boolean - =
or a $ \vee$ b bit, bit_vector, boolean - =
nand $ \neg$(a $ \wedge$ b) bit, bit_vector, boolean - =
nor $ \neg$(a $ \vee$ b) bit, bit_vector, boolean - =
xor a $ \neq$ b bit, bit_vector, boolean - =
Relational Operators
= a = b same type  
/= a $ \neq$ b same type  
< a < b same type  
<= a $ \leq$ b same type  
> a > b same type  
>= a $ \geq$ b same type  
Arithmetic Operators - Additive
+ a + b integer, real - =
- a - b integer, real - =
& a&b bit, bit_vector, character, string - same type
Arithmetic Operators - Sign
+ + a integer, real  
- - a integer, real  
Arithmetic Operators - Multiplicative
* a*b integer, real - =
/ a/b integer, real - =
mod a div b integer - =
rem a mod b integer - =
Other Operators
** ab integer, real - integer
abs | a| integer, real  
not $ \neg$a bit, bit_vector, boolean  

Since VHDL is a strongly typed language, it is sometimes useful to perform conversions between different types as well as explicitly specify the exact type that the expression should attain.

Qualified Expressions:
allow explicit specification of the type. This is helpful when there is no unambiguous classification of objects.

Syntax:
type'(expression)

Example:
type MONTH is (APRIL, MAY, JUNE);
type NAMES is (APRIL, JUNE, JUDY);

... MONTH'(JUNE) ...                     
for months
... NAMES'(JUNE) ...                      
for names

Conversions:
are used to convert an object of one type to another. Conversion functions for the standard types are predefined. A user is responsible for conversions between user-defined types.4

Example:
type FOURVAL is ('X', 'L,', 'H', 'Z');   
four-value logic
type VALUE4 is  ('X', '0,', '1', 'Z');   
..., different logic
...
function CONVERT4VAL (S: FOURVAL) return VALUE4 is
begin                            
conversion function
  case S is
    when 'X' => return 'X';
    when 'L' => return '0';
    when 'H' => return '1';
    when 'Z' => return 'Z';
  end case;
end CONVERT4VAL;
...
process (ABC)   
...calls the conversion function
  variable ABC: FOURVAL;
  variable XYZ: VALUE4;
...
  XYZ := CONVERT4VAL (ABC);
...

IEEE 1164 - Std_Logic_Vector
 Special operators are defined for the std_(u)logic_vector data type. In order to distinguish between unsigned and signed (2's complement) binary representations either explicit type conversion are required (see Section 2.5.3) or one of the two packages std_logic_unsigned or std_logic_signed must be used. These two packages as well as the basic package std_logic_1164 are defined in the IEEE library. They are especially useful for the evaluation of comparison operations. These packages are:

std_logic_1164
  logic and nand or nor xnor not
std_logic_unsigned / std_logic_signed
  relational = /= < <= > >=
  arithmetic + -, + - abs, *


In addition, these packages contain a number of conversion functions as well as shift operations for vectors.

Example:
library IEEE;                    
specify the Library
use IEEE.STD_LOGIC_1164.ALL;      
specify packages
use IEEE.STD_LOGIC_SIGNED.ALL;
...
  VARA := "1011";                     = -5
  VARB := "0011";                      = 3
  if (VARA > VARB) then                            false
  ...

If the unambiguous classification of an object with respect to the number system is not possible, as is the case with literal characters, subtypes (unsigned, signed) can be explicitly given.

Example:
signed'("1011") > signed'("0011")    false


next up previous contents
Next: 6. Sequential Modeling Up: Contents Previous: 4. Declarations and Identifiers
Richard Geissler
1998-10-07