A package is an element of VHDL that contains a collection of
commonly used declarations and subprograms. A package can also
be compiled and consequently used by more than one design or
entity. Following declarations may be placed in a package:
Packages can be (do not necessarily have to be) further subdivided into the declaration and the body. The declaration part consists of public, or visible to the rest of the design, information, such as the above mentioned declarations, which essentially define the interface for the package. The body contains the actual implementations, such as definitions of the objects found in the declaration. The advantage of keeping these two parts separate is fully realized by the ease of making changes during the reiteration of design cycles. Provided the interface is correct, only the body would need to be modified and re-analyzed. This is particularly beneficial in the following two cases (note that subprograms must be subdivided into the declaration and the body):
Syntax:
package package_name is
[type_decl]
[subtype_decl]
[constant_decl]
[deferred_constant_decl]
[subprogram_header_decl]
[component_decl]
end [package_name];
package body package_name is
[deferred_constant_value]
[subprogram_body]
end [package_name];
Packages, or rather their declarations, can be accessed from other design units with the use statement. To include only one element of a package, its name item_name must be specified at the end of the use statement. Usually several elements should be accessible. In this case the whole package can be included by specifying all at the end of the use statement. If the packages are not located in the library WORK (default), then the appropriate library_name must be explicitly specified.
Syntax:
[library library_name_list;] the default library is WORK
use [library_name.]package_name.item_name; |
[library_name.]package_name.all;
The desired elements of a package can be accessed by the item_name. If the name is not unique, e.g. because elements with the same name are defined in different packages, the elements must be explicitly called using the notation: [library_name.] package_name.item_name.
Example:
-- use of constant declarations --
package MY_DEFS is
constant UNIT_DELAY: time := 1 ns;
end MY_DEFS;
entity COMPARE is
port ( A, B:in bit;
C: out bit);
end COMPARE;
...
library DEMO_LIB; other than the default library WORK
use DEMO_LIB.MY_DEFS.all;
...
architecture DFLOW of COMPARE is
begin
C <= not (A xor B) after UNIT_DELAY;
end DFLOW;
...- deferred constant --
package MY_DEFS is
UNIT_DELAY: time; declaration only
end MY_DEFS;
package body MY_DEFS is
constant UNIT_DELAY: time := 1 ns; value assignment
end MY_DEFS;
-- subprogram --
package TEMPCONV is
function C2F (C: real) return real; declaration only
function F2C (F: real) return real;
end TEMPCONV;
package body TEMPCONV is
function C2F (C: real) return real is body of a function
begin
return (C * 9.0 / 5.0) + 32.0;
end C2F;
function F2C (F: real) return real is
...
Supplementary libraries and packages are used in the VHDL design for the following purposes:
The actual mapping of VHDL libraries on the file system of a computer is beyond the scope of the VHDL language. It is normally controlled by the computer system configuration files.