After the successful analysis of VHDL models, their simulation could be performed to verify the correct functionality. For this purpose, the elements in the lowest hierarchy level must be available as behavioral descriptions. Starting point of the simulation is the analyzed configuration declaration of a testbench or the top-level module.
Before the actual simulation takes place, the following two step are executed (without the interaction between the circuit developer and the simulation tool):
The simulation is usually done by stimulating the input signals of the unit under test (UUT) with the appropriate waveforms. This is easily achieved by the so-called testbench, a special entity which resides on top of the complete unit under test. The testbench generates the stimuli waveforms for the input signals of the unit under test by either a behavioral description or by reading them from a file. It is also possible to have the output signals from the UUT read, checked for correctness or written to a file by the testbench. Figure 9 illustrates the testbench concept.