Besides attributes associated with types, VHDL also provides attributes that are related to signals. Using these attributes it is possible to produce VHDL descriptions that take into consideration dynamic signal behavior. These attributes allow to incorporate simulation events and time instances at the time of simulation execution.
Syntax:
current point in time
signal'event true, if event (signal transition)
signal'active true, if transaction (signal assignment)
past events
signal'last_eventelapsed time from the last signal change
signal'last_valueprevious signal value
signal'last_activeelapsed time from the last signal assignment
Example:
entity DFLOP is D-Type FF
port ( CLK, D: in std_logic;
Q: out std_logic)
end DFLOP;
architecture BEHAV of DFLOP is
begin
process (CLK)
begin
if (CLK = '1') and CLK = 1
(CLK'event) and and a new event
(CLK'last_value = '0')
and previous value was 0 (because of `X`...)
then Q <= D;
rising edge
end if;
end process;