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4. Declarations and Identifiers

Identifiers are used to assign programmer defined names to objects. With the exception of a few reserved words, any word could be used. Following rules apply:

1.
Characters 'a'...'z', '0'...'9', '_'.
2.
the first character must be a letter.
3.
VHDL is not case sensitive.

When reference to Libraries and Packages is made, the complete object name must be given of the form:
lib_name.package_name.item_name

Comments:
start with two adjacent hyphens- and extend to the end of the line.
Constants:
assign a specific value to an object within a package, entity or architecture, and preserve it throughout the entire design.

Syntax:
constant identifier: type
[range_expr][:= expression];

Example:
constant Vcc:   real                         := 4.5;
constant CYCLE: time                         := 100 ns;
constant FIVE:  bit_vector                         := "0101";

Variables:
contain values assigned within a process. These are used sequentially according to the control flow. Variables can not be used to exchange information between different processes.

Syntax:
variable identifier_list: type
[range_expr][:= expression];
Variable declarations may specify the range of the data type and optionally initialize it to the desired value within that range.

Example:
variable INDEX:                  integer range 1 to 60 := 27;
variable CYCLE_TIME:                  time range 10 ns to 50 ns := 10 ns;
variable REGISTER:                  std_logic_vector (7 downto 0);

Signals:
connect together Design-Entities and propagate value changes within a design. They are the primary means of communication between processes.3

Syntax:
signal identifier_list: type
[range_expr][:= expression];
Signal declaration may specify the range of the data type and optionally initialize it to the desired value within that range.

Example:
signal COUNT:     integer range 1 to 31;
signal GROUND:    bit := '0';
signal INT_BUS:  std_logic_vector (1 to 8);
Caution:
Signals can not be declared within a process. They can be used within a process; however, signal value assignment occurs in the simulation time. That is, signal values are not updated in the sequential order, as is the case with variables, rather at the wait-Statement. At this point the signal acquires a value assigned to it immediately before the wait-Statement.

Signal assignments are using special operators to indicate their peculiar time behavior. Explicitly stated signal assignment delays take effect during the simulation:


signal xyz: bit;
...
xyz <= '1' after 5 ns;

The use of signals in the sequential flow of processes often produces unanticipated erroneous results. Therefore, it is recommended to use variables in the sequential flow of a process (with read and write operations) and then to assign newly computed values to signals just before the next wait statement.

Two additional remarks regarding the variables and signals:
Initialization:
variables and signals that are not explicitly initialized during the declaration receive default values according to the following rules:


Enumerated types : the first values in the list
integer, real : the lowest allowable value



The initialization of enumerated types is often used, for example, by defining the desired initial state of finite state machines as the first one in the list of states, or with std_logic where the special value 'U' (uninitialized) is assigned to every signal/variable without an explicit initial value.

it may be desirable to start with 'U' (uninitialized) value.

Range constraints:
in order to obtain correct hardware synthesis results, variables and signals must be constrained to the desired bit-width. This is especially critical with the unspecified integer-type synthesis, where a default 32-bit datapath is generated.

Example:
signal CNT100:    integer range 0 to 99;   
unsigned 7-bit
signal ADDR_BUS: std_logic_vector (7 to 0);   
8-bit


next up previous contents
Next: 5. Expressions and Operators Up: Contents Previous: 3.5 Type and Field
Richard Geissler
1998-10-07