next up previous contents
Next: 9. Structural Descriptions Up: Contents Previous: 7.4 Signal Attributes

8. Concurrent Modeling

Concurrent statements serve to model the behavior of hardware components where events often occur simultaneously.

Process:
  A process as a whole is treated as a concurrent assignment. It was already presented as a module which contains a set of sequentially executed statements.8 It has the following features:


- all processes are active in parallel.
- a process defines a region in the code where statements are executed sequentially (similarly to the conventional programming languages). It describes behavior employing sequential algorithms.
- a process must contain either a sensitivity-list or explicit wait statements.
- within a process, signals belonging to an entity or architecture could be read and assigned new values.
Process Execution
Since processes are supposed to model the behavior of hardware elements which in real-world are always active, VHDL processes possess some special features.
Execution:
A process can be viewed as a forever loop. At the beginning of the simulation, as some sort of initialization, every process is activated and executed up to the first wait. Subsequently, the execution of processes suspends according to the conditions enforced by the wait statements. Processes whose conditions of wait statements are satisfied, are re-activated. They continue the execution of statements in sequential order until the next wait statement suspends them. If the end of a process is reached (end process;), the execution continues from the beginning of a process. This is illustrated by the following example:

Example:
process ...
begin
  loop                         
beginning of the loop
    ...
    wait ...   
at least one wait, or a sensitivity-list
    ...
  end loop;                          
end of the loop
end process;

Activation:
As mentioned above, the simulator executes a process sequentially, statement by statement. It is then suspended at one or more locations by the waits. The execution is again re-activated by the arrival of specific events.

It follows then, that a process must have at least one wait statement, or a process must be declared with a sensitivity-list. The sensitivity-list is functionally equivalent to a waiton... statement appearing at the end of a process.

Example:
process (A, B)                      
sensitivity-list
begin
  ...
end process;

-- is equivalent to --
process
begin
  ...
  wait on A, B;
end process;

When describing a data flow, each transaction would correspond to a process, which contains only one statement inside. There is a simpler way to model this by using concurrent assignments. These assignments are located within an architecture and each of them corresponds to a process. The order of concurrent assignments in VHDL is irrelevant.
Concurrent Signal Assignment:
is functionally equivalent to a process which contains only one statement and has a sensitivity-list.

Syntax:
[label:] signal_name <= expression [after time_expr];
The assignment is activated when at least one signal on the right side of the assignment statement changes.

Example:
architecture VER1 of MUX is
begin
  OUTPUT <= A (INDEX);
end VER1;

-- is equivalent to --
architecture VER1 of MUX is
begin
  process (A, INDEX)
  begin
    OUTPUT <= A (INDEX);
  end process;
end VER1;

Selected Signal Assignment:
corresponds to a process with a single signal assignment which is enabled through the case statement.

Syntax:
[label:] with expression select
  signal_name <=expression when value{,
                expression when value};
The selected signal assignment is activated as soon as one of the signals belonging to the selection condition or expression changes.

Example:
with MYSEL select
  Z <=  A when 15,
        B when 22,
        C when 28;

Concurrent Procedure Call:
is equivalent to a process which contains only one statement -- a procedure call. The procedures' parameters are of one of the following modes: in, out or inout. When one of the parameter signals changes, the procedure call is activated.

Example:
architecture ...
  procedure VEC2INT
    ( signal S: in bit_vector;
      signal ZFLAG: out boolean;
      signal Q: inout integer;) is
  ...
begin
  VEC2INT (BITVEC, FLAG, NUMBER);
  ...

-- is equivalent to --
architecture ...
  procedure VEC2INT ...   
declaration, same as above
begin
  process (BITVEC, NUMBER)
  begin
    VEC2INT (BITVEC, FLAG, NUMBER);
  end process;
  ...

Block:
In order to efficiently group concurrent assignments, block statements may be used. A block may contain declarations of data types, signals, and so on, all of which are locally used. The body of the block statement contains any of the concurrent statements mentioned previously. 

A guarded block contains an additional boolean expression guard_expression, which drives an implicit signal GUARD of boolean type. This signal can be used within a block for the control of concurrent assignments. If concurrent statements have an associated GUARD signal, they are known as Guarded Signal Assignments.

Syntax:
label: block
[(guard_expression)]
  
[use_clause]
  
[subprogram_decl subprogram_body]
  
[type_decl]
  
[subtype_decl]
  
[constant_decl]
  
[signal_decl]
  
[component_decl]
begin
  
[concurrent_statements]
end block
[label];

Guarded Signal Assignment:
is a special form of the concurrent assignment. The assignment is activated after the GUARD signal, which must be of the boolean type, is evaluated to true. The GUARD signal can be explicitly declared and used; however, it is more common to use it implicitly within a Guarded Block.

Syntax:
[label:] signal_name <= guarded expression [after time_expr];

Conditional Signal Assignment:
is equivalent to a process with a single if statement and a signal assignment. Building complex if...elsif... conditions is also allowed.

Syntax:
[label:] signal_name <=expression when condition else
                    {expression when condition else}
                    expression;
The conditional signal assignment is activated as soon as one of the signals belonging to the condition or expression changes.

Example:
Z <=  A when (X > 3) else
      B when (X < 3) else
      C;


next up previous contents
Next: 9. Structural Descriptions Up: Contents Previous: 7.4 Signal Attributes
Richard Geissler
1998-10-07