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1.1 Motivation: IC Design Methodologies

In the last twenty years a change took place in the methodology of digital circuits design. In the past, integrated circuits were manually composed with graphical CAD-tools. For that purpose basic elements (logic gates from a library, or rather their symbols) had to be selected, placed on a schematic and connected with each other. In this way simple modules could be created which were then used to assemble complex circuits. This methodology is called bottom-up. It could take a long time to generate large circuits and the result was difficult to change because this meant laborious redrawing of the schematics.

Today, designing electrical systems deals with more and more complex systems, which can be integrated in single chips due to the increasing packing density. A short development cycle is another decisive factor designers have to consider in order to stay on top of the competition and to satisfy the requirements of the customers. Therefore, the reuse of once generated functional blocks and module in new systems is important. This requires a technology independent description of the circuits.

As far as digital circuits are concerned, the above considerations lead to the adoption of a top-down design flow. Using hardware description languages, modeling of systems at various levels of abstraction is possible. Due to the stepwise refinement in the top-down design flow, such a description language has to support all levels of abstraction: system specification, algorithmic description, functional blocks, and gate-level netlists. An important aspect in today´s design flows is the use of synthesis tools which automatically create gate-level netlists from behavioral descriptions. This requires a standardized language which would allow the simulation of the modeled system at different levels of abstraction.

VHDL (VHSIC Hardware Description Language; VHSIC (Very High Speed Integrated Circuit)) meets all these requirements. It is possible to describe concurrent or sequential behavior of digital circuits, with or without timing, at various levels of abstraction. Hierarchical designs may be created by instantiating submodules and connecting them with each other. Nowadays, the language is supported by all major design tools mainly because it was standardized by the IEEE. Therefore, it can be used as an exchange medium between different CAD tools, or CAD tool users and chip vendors.

VHDL was initiated in the early 80's under the VHSIC program in the USA. The aim of this program was to develop a hardware description language for unambiguous documentation of digital systems. At that time, a number of companies designed VHSIC chips for the Department of Defense. Each used a different description language for developing and modeling their circuits. Data exchange, reuse and reproduction of designs was a big issue under these conditions. After the public release of VHDL in 1985 and additional enhancement in the following two years, VHDL was standardized by the IEEE in December 1987. It has also been recognized as an American National Standards Institute (ANSI) standard. The official language description appears in the IEEE Standard VHDL Language Reference Manual (LRM). According to IEEE rules, it has to be reviewed every five years. This lead to the latest IEEE Standard, known as Std 1076-1993.


next up previous contents
Next: 1.2 Contents and Structure Up: 1. Introduction Previous: 1. Introduction
Richard Geissler
1998-10-07