A description style where different components of an architecture and their interconnections are specified is known as a VHDL structural description. Initially, these components are declared and then components' instances are generated or instantiated. At the same time, signals are mapped to the components' ports in order to connect them like wires in hardware. VHDL simulator handles component instantiations as concurrent assignments.
Syntax:
component declaration:
component component_name
[generic (generic_list: type_name [:= expression] {;
generic_list: type_name [:= expression]} );]
[port (signal_list: in|out|inout|buffer type_name {;
signal_list: in|out|inout|buffer type_name} );]
end component;
component instantiation:
component_label: component_name port map (signal_mapping);
The mapping of ports to the connecting signals during the instantiation can be done through the positional notation. Alternatively, it may be done by using the named notation, using the already familiar format:
Syntax:
If one of the ports has no signal connected to it (this happens, for example, when there are unused outputs), a reserved word open may be used. A function call can replace the signal name. This allows direct type conversions at the component instantiation.
Example:
signal_mapping: declaration_name => signal_name. entity RSFF is
port ( SET, RESET: in bit;
Q, QBAR: inout bit);
end RSFF;
architecture NETLIST of RSFF is
component NAND2
port (A, B: in bit; C: out bit);
end component;
begin
U1: NAND2 port map (SET, QBAR, Q);
U2: NAND2 port map (Q, RESET, QBAR);
end NETLIST;
-- named notation instantiation: --
U1: NAND2 port map (A => SET, C => Q, B => QBAR);
![]() |